This invention relates to a new method and apparatus for use in a processor-based system, to prevent data corruption during the postamble phase of a memory access command. In particular, a system is described that prevents a tristate of a postamble of a command for access to a DDR (double data rate) DRAM device from corrupting data being read from or written to that device.
During a read access from a DDR DRAM device, read data is provided by the device (e.g. a DIMM, or dual in-line memory module) in response to a clock forwarded from the device. The read data is captured by the memory controller's storage elements with this forwarded clock.
In the JEDEC specification entitled “Double Data Rate (DDR) SDRAM Specification” (JESD79), incorporated herein by reference, the forwarded clock is referred to as the “DQS” signal, and the data provided by the DRAM device such as a DIMM is designated by “DQ”. An example of how data is clocked according to the DDR SDRAM specification is shown in FIG. 1, where a DQS preamble 1 is shown, followed by clock cycles 10, 20 and 30, and followed by DQS postamble 2. The clock cycles 10, 20 and 30 includes rising edges 10R, 20R and 30R and falling edges 10F, 20F and 30F, respectively.
In double data rate reads, data is read both on the rising edge and the falling edge of a clock signal. Thus, in FIG. 1, data units (e.g. words, bytes, quad words, etc.) 40-90 are read out from the DRAM device on each edge of clock cycles 10-20. Data unit 40 is read out on the rising edge of clock cycle 10, data unit 50 is read out on the falling edge of clock cycle 10, data unit 60 is read out on the rising edge of clock cycle 20, etc.
The preamble 1 and postamble 2 are defined to be stable LOW states for the DQS signal. Before the preamble and after the postamble, the DQS signal is considered “tristate”, meaning that it is not driven either high or low, and may fluctuate from one state to another. Because of this fluctuation, a DQS in tristate could corrupt the read data storage elements by driving them in an unpredictable fashion, e.g. during the postamble period, after a read data command has been issued but before the requesting device has captured the data read out from the DRAM device (e.g. in FIG. 1, before the requesting device has captured data unit 90).
This likelihood of corruption of data by a tristate postamble signal is increased in systems that use double data rate reads, such as in the manner specified in the JEDEC DDR DRAM specification. An architecture and method are therefore needed for such systems that will avoid this data corruption problem, without compromising the ability to read or write data at speeds otherwise allowed by a DDR scheme.
In particular, a design is needed that will prevent a postamble signal from driving memory devices that contain data read from or written to a DDR DIMM or other DDR device, before that data has been captured by the requesting device.